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Package
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Categories Typical Sample
(not to scale)
Pin Counts Lead Pitches [mm] Remarks Capacity (pF) Inductance (nH)
DIL or DIP
(Dual-in-line Package)
8, 14, 16,18, 20, 22, 24, 28, 32, 36, 40, 42, 48 2.54 100mil pitch type 1 – 10 5 – 40
SDIL or SDIP
(Shrink Dual-in-line Package)
30, 42, 64 1.778 70mil pitch type 1 – 10 1 – 10
ZIP
(Zig-Zag In-line Package)
20, 24, 28, 40 1.27 50mil pitch type
SOP
(Small Outline Package)
8, 16, 24, 28, 32, 40, 44 1.27 1 – 7 1 – 7
SSOP
(Shrink Small Outline Package)
20, 28, 30, 32, 60, 64, 70 0.65, 0.80, 0.95, 1.00 heat-resistant
TSOP(1)
(Thin Small Outline Package)
32, 48 0.50 leads on short side
QFP
(Quad Flat Package)
44, 56, 64, 80, 100, 128, 160, 208, 240, 272, 304 0.50, 0.65, 0.80, 1.00 heat-resistant 2 – 5 3 – 7
LQFP
(Low Profile Quad Flat Package)
144, 176, 208 0.50 1.4mm body thickness
TQFP
(Thin Quad Flat Package)
44, 48, 64, 80, 100, 120, 128 0.50, 0.80 1.20mm body thickness
SOJ
(Small Outline J-lead)
26, 26(20), 26(24), 28, 28(24), 32, 36, 40, 42, 50 0.80, 1.27 Two J-lead lead rows
QFJ
(Quad Flat J-lead)
18, 20, 22, 28, 32, 44, 68, 84 1.27 50mil pitch type, formerly PLCC, Four J-lead lead rows
BGA
(Ball Grid Array)
256, 352, 420, 560 1.00, 1.27 Epoxy package, SnPb balls 1 – 10 0.5 – 10
FBGA
(Fine Ball Grid Array)
48, 84, 104, 144, 176, 224 0.80 Epoxy package, SnPb balls 1 – 20 0.5 – 10
FLGA
(Fine Land Grid Array)
49, 56, 84 0.80 Epoxy package, Au-plated lands
CSP
(Wafer-level Chip Scale Package)
47, 48, 111, 141, 160 0.40, 0.50, 0.80 Packaged wafer cut into chips 1 – 15 0.5 – 5

package outlines and dimensions.pdf



ON semi data. cf: AND8009

PackageR (ohm)L (nH)C (pF)
SOIC-81.50.188
TSSOP-80.0481.90.089
SOIC-20 W0.1363.040.158
TSSOP-200.0331.760.98
QFN-240.0551.290.05
LQFP-320.672.380.13
LQFP-520.883.30.072
LQFP-640.100.670.05
QFN-160.0390.750.13
QFN-320.421.390.142
TSSOP-100.0481.90.089
SOIC-160.1522.7140.364
TSSOP-160.0440.82 0.41